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<div class="header">
  <div class="headertitle"><div class="title">LTDC_TypeDef Struct Reference<div class="ingroups"><a class="el" href="group___c_m_s_i_s___device.html">CMSIS_Device</a> &raquo; <a class="el" href="group__stm32h723xx.html">Stm32h723xx</a> &raquo; <a class="el" href="group___peripheral__registers__structures.html">Peripheral_registers_structures</a></div></div></div>
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<p>LCD-TFT Display Controller.  
 <a href="#details">More...</a></p>

<p><code>#include &lt;<a class="el" href="stm32h723xx_8h_source.html">stm32h723xx.h</a>&gt;</code></p>
<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 id="header-pub-attribs" class="groupheader"><a id="pub-attribs" name="pub-attribs"></a>
Public Attributes</h2></td></tr>
<tr class="memitem:a1a43b1a297bbe2126e6697a09d21612d" id="r_a1a43b1a297bbe2126e6697a09d21612d"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a1a43b1a297bbe2126e6697a09d21612d">RESERVED0</a> [2]</td></tr>
<tr class="memitem:aa5bb98a48470eaf50559e916bce23278" id="r_aa5bb98a48470eaf50559e916bce23278"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#aa5bb98a48470eaf50559e916bce23278">SSCR</a></td></tr>
<tr class="memitem:aefc3daf9db06d441115572be02bb49bd" id="r_aefc3daf9db06d441115572be02bb49bd"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#aefc3daf9db06d441115572be02bb49bd">BPCR</a></td></tr>
<tr class="memitem:a20602a2e34b3e4e97e07474e5ad9c22b" id="r_a20602a2e34b3e4e97e07474e5ad9c22b"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a20602a2e34b3e4e97e07474e5ad9c22b">AWCR</a></td></tr>
<tr class="memitem:a7a7b8762321bdcdc8def7a6ace94a455" id="r_a7a7b8762321bdcdc8def7a6ace94a455"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a7a7b8762321bdcdc8def7a6ace94a455">TWCR</a></td></tr>
<tr class="memitem:a154e0514cfca7449156dd5a9133631ac" id="r_a154e0514cfca7449156dd5a9133631ac"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a154e0514cfca7449156dd5a9133631ac">GCR</a></td></tr>
<tr class="memitem:aadd4b8262474fe610f5414e1ff2fbcbe" id="r_aadd4b8262474fe610f5414e1ff2fbcbe"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#aadd4b8262474fe610f5414e1ff2fbcbe">RESERVED1</a> [2]</td></tr>
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<tr class="memitem:ae3e85d4ed370a42e7fd46d059dffaaa8" id="r_ae3e85d4ed370a42e7fd46d059dffaaa8"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ae3e85d4ed370a42e7fd46d059dffaaa8">RESERVED2</a> [1]</td></tr>
<tr class="memitem:acf20a59c07d3e013d0207b1719b973b6" id="r_acf20a59c07d3e013d0207b1719b973b6"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#acf20a59c07d3e013d0207b1719b973b6">BCCR</a></td></tr>
<tr class="memitem:afffbe3c266a4f2bd842eb96103b65dac" id="r_afffbe3c266a4f2bd842eb96103b65dac"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#afffbe3c266a4f2bd842eb96103b65dac">RESERVED3</a> [1]</td></tr>
<tr class="memitem:a0ab6c92574cc246707aa1371e3c5cb85" id="r_a0ab6c92574cc246707aa1371e3c5cb85"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a0ab6c92574cc246707aa1371e3c5cb85">IER</a></td></tr>
<tr class="memitem:a2e3f3fba908b85d2fcf1eaab6b5600bf" id="r_a2e3f3fba908b85d2fcf1eaab6b5600bf"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a2e3f3fba908b85d2fcf1eaab6b5600bf">ISR</a></td></tr>
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<tr class="memitem:af019d85ce2b876ee99d994a09de12ec3" id="r_af019d85ce2b876ee99d994a09de12ec3"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#af019d85ce2b876ee99d994a09de12ec3">CPSR</a></td></tr>
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</table>
<a name="details" id="details"></a><h2 id="header-details" class="groupheader">Detailed Description</h2>
<div class="textblock"><p>LCD-TFT Display Controller. </p>
</div><a name="doc-variable-members" id="doc-variable-members"></a><h2 id="header-doc-variable-members" class="groupheader">Member Data Documentation</h2>
<a id="a20602a2e34b3e4e97e07474e5ad9c22b" name="a20602a2e34b3e4e97e07474e5ad9c22b"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a20602a2e34b3e4e97e07474e5ad9c22b">&#9670;&#160;</a></span>AWCR</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t LTDC_TypeDef::AWCR</td>
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<p>LTDC Active Width Configuration Register, Address offset: 0x10 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#acf20a59c07d3e013d0207b1719b973b6">&#9670;&#160;</a></span>BCCR</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t LTDC_TypeDef::BCCR</td>
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<p>LTDC Background Color Configuration Register, Address offset: 0x2C </p>

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<a id="aefc3daf9db06d441115572be02bb49bd" name="aefc3daf9db06d441115572be02bb49bd"></a>
<h2 class="memtitle"><span class="permalink"><a href="#aefc3daf9db06d441115572be02bb49bd">&#9670;&#160;</a></span>BPCR</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t LTDC_TypeDef::BPCR</td>
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<p>LTDC Back Porch Configuration Register, Address offset: 0x0C </p>

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<a id="a6d6675f23322e241122468935ee60ed1" name="a6d6675f23322e241122468935ee60ed1"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a6d6675f23322e241122468935ee60ed1">&#9670;&#160;</a></span>CDSR</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t LTDC_TypeDef::CDSR</td>
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<p>LTDC Current Display Status Register, Address offset: 0x48 </p>

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<a id="af019d85ce2b876ee99d994a09de12ec3" name="af019d85ce2b876ee99d994a09de12ec3"></a>
<h2 class="memtitle"><span class="permalink"><a href="#af019d85ce2b876ee99d994a09de12ec3">&#9670;&#160;</a></span>CPSR</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t LTDC_TypeDef::CPSR</td>
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<p>LTDC Current Position Status Register, Address offset: 0x44 </p>

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<a id="a154e0514cfca7449156dd5a9133631ac" name="a154e0514cfca7449156dd5a9133631ac"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a154e0514cfca7449156dd5a9133631ac">&#9670;&#160;</a></span>GCR</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t LTDC_TypeDef::GCR</td>
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<p>LTDC Global Control Register, Address offset: 0x18 </p>

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<a id="a7c7225eb9029a81f17b60cf4104eaffb" name="a7c7225eb9029a81f17b60cf4104eaffb"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a7c7225eb9029a81f17b60cf4104eaffb">&#9670;&#160;</a></span>ICR</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t LTDC_TypeDef::ICR</td>
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<p>LTDC Interrupt Clear Register, Address offset: 0x3C </p>

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<a id="a0ab6c92574cc246707aa1371e3c5cb85" name="a0ab6c92574cc246707aa1371e3c5cb85"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a0ab6c92574cc246707aa1371e3c5cb85">&#9670;&#160;</a></span>IER</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t LTDC_TypeDef::IER</td>
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<p>LTDC Interrupt Enable Register, Address offset: 0x34 </p>

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<a id="a2e3f3fba908b85d2fcf1eaab6b5600bf" name="a2e3f3fba908b85d2fcf1eaab6b5600bf"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a2e3f3fba908b85d2fcf1eaab6b5600bf">&#9670;&#160;</a></span>ISR</h2>

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<p>LTDC Interrupt Status Register, Address offset: 0x38 </p>

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<a id="a74a5f74bb4f174bbda1e2dc3cce9f536" name="a74a5f74bb4f174bbda1e2dc3cce9f536"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a74a5f74bb4f174bbda1e2dc3cce9f536">&#9670;&#160;</a></span>LIPCR</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t LTDC_TypeDef::LIPCR</td>
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<p>LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a1a43b1a297bbe2126e6697a09d21612d">&#9670;&#160;</a></span>RESERVED0</h2>

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          <td class="memname">uint32_t LTDC_TypeDef::RESERVED0[2]</td>
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<p>Reserved, 0x00-0x04 </p>

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<a id="aadd4b8262474fe610f5414e1ff2fbcbe" name="aadd4b8262474fe610f5414e1ff2fbcbe"></a>
<h2 class="memtitle"><span class="permalink"><a href="#aadd4b8262474fe610f5414e1ff2fbcbe">&#9670;&#160;</a></span>RESERVED1</h2>

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<p>Reserved, 0x1C-0x20 </p>

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<p>Reserved, 0x28 </p>

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<p>Reserved, 0x30 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a502dd9d2d17025a90bdf968eb29827f2">&#9670;&#160;</a></span>SRCR</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t LTDC_TypeDef::SRCR</td>
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<p>LTDC Shadow Reload Configuration Register, Address offset: 0x24 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#aa5bb98a48470eaf50559e916bce23278">&#9670;&#160;</a></span>SSCR</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t LTDC_TypeDef::SSCR</td>
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<p>LTDC Synchronization Size Configuration Register, Address offset: 0x08 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a7a7b8762321bdcdc8def7a6ace94a455">&#9670;&#160;</a></span>TWCR</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t LTDC_TypeDef::TWCR</td>
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<p>LTDC Total Width Configuration Register, Address offset: 0x14 </p>

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<hr/>The documentation for this struct was generated from the following file:<ul>
<li>C:/Users/ASUS/Desktop/dm-ctrlH7-balance-9025test/Drivers/CMSIS/Device/ST/STM32H7xx/Include/<a class="el" href="stm32h723xx_8h_source.html">stm32h723xx.h</a></li>
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